“Recommendations and Roadmap for European Sovereignty in open source HW, SW and RISC-V Technologies” document from 2021 calls for the development of critical open source IP blocks within 2-5 years. PCIe Root Complex (RC) is one of them.

This project is the first step in that direction.

It aims to open Artix7 PCIe Gen2 RC for use outside of proprietary tool flows. While still reliant on Xilinx Series7 Hard Macros (HMs), it will surround them with open-source Soft IP for PIO accesses — The RTL and, even more importantly, the layered Driver Software with 1-port Demo App.

The project‘s immediate goal is to empower the makers with ability to host PCIe-based peripherals on their RISC-V SOCs. Since End-Point (EP) with DMA is already available, open-source PCIe peripherals do exist for Artix7. Except that they are always, without exception, controlled by the proprietary RC on the motherboard side. This project intends to change that status quo.

The long-term goal is to set the stage for the development of full open-source PCIe stack, and gradually phase out Xilinx HMs from the solution. That’s a long, ambitious path, esp. when it comes to mixed-signal SerDes and high-quality PLLs. We therefore anticipate a series of follow on projects that would build on the foundations we hereby set.

Project is currently in the planning phase.

Stay tuned for updates…