Open hardware

Your FPGA

in control of

your PCIe

Enter openPCIE backplane, the hardware backbone of PCIe systems built around your own plug-and-play host.

Most, if not all, commercial PCIe plug-in cards are wired as Endpoints. All PC mobos have their Root Complex soldered down, with their PCIe connectors designed to accept only the Endpoint plug-in cards. The two ends of the PCIe link indeed fully reinforce this state of affairs:

THE READILY AVAILABLE PCIe PLUG-IN CARDS ARE MADE TO BE ENDPOINTS. Period.

Why and When would you need this backplane?

• ✦To test your Root Complex PCIe protocol stack using a standard EndPoint Slot or M.2 card.
• ✦To build your custom PCIe embedded systems with plug-and-play (therefore easy) Host upgrades and repairs.
• ✦For anything else that crosses your mind and puts your creativity and our card to good work.

Honestly, this piece of FR4 is unique.

We’ve spent a ton of time looking for a ready-made board in the likes of this backplane. Our original project goal was not to develop PCBs, but the RTL for an opensource PCIe RC and off-the-shelf Artix7 plug-in card.

Having found nothing on the civilian market, we bit the bullet and put in a bunch of extra work to design and validate this one-of-a-kind backplane — Not the VME/VPX, but a distant look in that direction, fully in opensource, ready for the makers, hobbyists, researchers, students, …

By Chili.CHIPS · Together with Envox d.o.o.

All PCIe expansion cards expect a motherboard to be in charge. The motherboard supplies reference clock and reset. Its Root Complex discovers devices and manages communication. That works well when you are developing PCIe peripherals. Building a PCIe Host itself is a whole another game.

openPCIE provides the ecosystem that Endpoint cards need, and removes mobo RC out of the way. Plug-in an off-the-shelf FPGA card, load a Root Complex design into it, then plug-in an Endpoint. Or, yet better, load Endpoint bit file into the second, identical FPGA card. You can now develop for both ends of the link, inspect the transactions, experiment with software that controls them, …

The idea that makes it possible

An Endpoint card. A Root Complex role.

The RC connectors cross the Tx and Rx diff pairs, thus an ordinary plug-in card (= Endpoint pinout) can now be used as the Host. Clock and reset are supplied by our backplane.

The FPGA still needs RC stack and Host software — The connector wiring enables only the physical connection; it does not turn an arbitrary PCIe peripheral into a Host. But, our repo has fully worked out examples, along with sim setup, for both FPGA loads: RC and EP.

Our RC CPU is not an x86 or ARM. It is a soft RISC-V inside the FPGA. Still, you can plug-in the PC or RPi and have them take on the Host role instead of FPGA.

POINT TO POINT ISLAND

Direct connection

An M.2 M-key Root Complex connector links directly to a standard PCIe Endpoint slot. This is the simplest and highest performing setup. We used it for initial testing of link training, enumeration and data transfer between two devices.

The direct connection has been successfully proven for Gen2 x4, with all four PCIe lanes active.

SWITCHED FABRIC ISLAND

Four downstream ports

An ASMedia ASM1184e PCIe 2.0 switch connects one upstream x1 link to four downstream x1 links. The provides two standard Slots and two M.2 M-key sockets.

All four ports share the upstream x1 bandwidth; adding ports does not multiply the host link’s capacity.

01

Develop an FPGA Root Complex

Bring up a host design on a compatible FPGA, enumerate a peripheral and exercise Memory Read and Memory Write transactions. Use the direct island to keep the first experiments focused.

02

Connect a RISC-V system

Explore the broader openPCIE project’s soft RISC-V SoC, bare-metal driver and test application. Follow the path from software register accesses to PCIe traffic on real hardware.

03

Investigate switched systems

Add endpoints behind the ASM1184e and work through bridge discovery, resource assignment and shared upstream bandwidth. Device support depends on the host implementation and drivers.

04

Teach the complete stack

Give students access to the schematics, PCB, RTL, driver and simulation environment. Trace how power, reset, clocks, packets and software combine into a working system.

05

Evaluate interoperability

Use the backplane as a platform for planned cross-vendor work, including the related openCologne-PCIE Endpoint project. Compatibility must be established for each FPGA and configuration.

06

Extend a test setup

The repository also describes a PCIe jumper-cable approach for a conventional host. Follow its wiring and clocking requirements when exploring expansion or physical extension.

04 / Engineered in the open

The SI magic behind the connections

The KiCad design uses a four-layer stackup with ground and 3.3 V reference planes. High-speed differential pairs are routed as microstrips, with attention to skew, vias and connector stubs.

The PCB documentation specifies a 100 Ω ±10% differential-impedance target for data and clock signals and no more than 5 mil P-to-N skew. These are layout targets, not a substitute for measured compliance results.

A dedicated 100 MHz clock source and differential distribution support the cards. Clock-request handling and a push-button reset make repeated bring-up experiments practical.

Read the PCB design notes →

EXISTING HOST

Conventional PCIe expanders

Products such as Waveshare’s PCIe-Packet-Switch-4P expand a host connection into four Gen2 x1 sockets. That is useful when the host is already chosen and the goal is to attach more peripherals.

SINGLE-BOARD COMPUTER

Open Raspberry Pi hubs

The open PCIe3_Hub project is an example of an ASM2806-based design using Raspberry Pi 5 FPC connectors. It shows that openness alone is not the differentiator.

YOUR OWN HOST

The openPCIE approach

RC connector routing, onboard supporting circuits, a direct four-lane path and a separate switched island are combined for FPGA host experiments. The surrounding openPCIE project adds RTL, software and co-simulation to help you explore the whole system.

HARDWARE

Schematics, PCB and BOM

Browse the PCB source for KiCad files, the schematic PDF, bill of materials, component references and test procedure. The published schematic carries a CERN-OHL-P v2 notice.

LOGIC + SOFTWARE

Follow a PCIe transaction end-to-end

Explore the main project for the Artix-7 Root Complex work, a soft RISC-V SoC, bare-metal software, build instructions and the demonstration setup. Consult each file’s license when reusing it.

VERIFICATION

Simulate before the bench

Open the co-simulation environment to study the VProc / pcieVHost-based testbench and its CPU options. The current FPGA approach still uses AMD/Xilinx hard PCIe and transceiver blocks; removing those dependencies is a longer-term goal.

For a first direct-link experiment, plan for the backplane, a compatible RC-capable FPGA module, a suitable Endpoint, the required adapters, a correctly wired 12 V supply and a programming/debug connection. The repository demonstrates Acorn CLE-215+ modules and separate JTAG programmers.

Program the RC and EP designs, apply the documented reset sequence and verify link status before testing payload transfers. The driver and test application provide a starting point for enumeration and memory transactions.

Check clock-request wiring. The prototype report found that some older M.2-to-PCIe adapters did not carry CLKREQ#. Follow the documented solution for your exact board revision and adapter.

Before choosing cards

Form factor is only the first check. Confirm connector role, lane count, power budget, reference clock, reset behavior and software support.

Choose PCIe M-key devices supported by your FPGA host design and software.

The approximately 70 W total power budget is shared across the backplane and connected devices. Check each device’s power requirements when planning your setup.

11 / The next chapter

Bring openPCIE to your lab bench

We are preparing the next step for the openPCIE Backplane on Crowd Supply. Explore the working hardware and open documentation now, and check the campaign details here as they are finalized.

CROWD SUPPLY / CAMPAIGN DETAILS

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