The Faculty of Electrical Engineering University of Sarajevo is, within the framework of ETFPGA student club, developing eduBos5 — Their own RISC5 CPU with educational focus, cleanly written in the full complement of SystemVerilog, step-by-step introducing HDL, STA, Digital Design and Verification concepts through practical work on the carefully constructed labs. All well explained, documented and packaged with scripts and demos for 高云半导体 Gowin Semiconductor Corp platform, while also tapping into open-source Verilator, GTKWave and MSYS2.

Boasting super-readable, easy to follow and comprehend RTL coding, this design lends itself to modifications/optimizations to specific embedded tasks. Be it by adding own instruction(s), or complete co-processor, the overall architecture is envisioned as a flexible ecosystem for accelerated execution of the program at hand.

>>> Which brings us to proBos5 <<<

Our proBos5 offering is of commercial nature and means the capacity to, using FPGA of your choice, ASIC of your process node, EDA tool chain of your preference, solve your application problem with the exact fit of a custom-tailored execution pipeline.