Spicing up the first and only EU FPGA with cool demos, real examples and a hot new board.
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Recent appearances of affordable boards with CologneChip GateMate FPGA, most notably from Olimex and Trenz, emphasize the urgency of need for good, well documented real-life examples.
Thanks to GateMate’s modularity /* 1, 2, or 4 FPGA chiplets on a shared interposer */, its compute potential can scale from 20K, 40K to 80K 8-input MUX trees. Double these numbers for the 4-input baseline combos: 40K, 80K, 160K are also the flop counts!
Even higher densities are on the roadmap.
GateMate is one of the rare families designed around 8-input combo MUX trees, and not the mainstream LUTs!
To be fully fair, this gain in combo capability is offset by the loss of Distributed RAM resources, the alter ego of LUT micro-RAM elements.
Before we get to them, you can get a feel for the examples here:
And, until we create all relevant drawings and pictures, the concept of ULX5M board can be grasped by looking at the rendition of ULX4M on a commercial CM4 RPi baseboard.
Then imagine the ULX5M in its place, with Cologne Cathedral instead of Lattice logo on the FPGA, and one important change in the storage department — To counter lower GateMate pin count, we must replace two ULX4M:
- Lattice + SDRAM (-LS)
- Lattice + DDR3 (-LD)
options with one-and-only-one type of external memory: HyperRAM. Hence the ULX5M-CH designation, conveying that this 5th member of the ULX family feeds on Cologne logic and Hyper memory.
ULX5M-CH is intended to be more affordable and more accessible than its older sibling.
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This ULX4M <-> ULX5M swap-ability objective shall be made transparent to base board, even for SerDes. Yes, GateMate can do multi-gigabit serial!
Yet, it will take some hard work to accomplish our plug-and-play goal, which we plan to reach step-by-step, by porting the peripherals one at a time, aided by an assortment of PMODs, some even made from the scratch.
In the end, as the proverbial cherry on top of the cake goes, we are imagining either ULX4M or ULX5M on top of the BB3-CM4 :> Pick your favorite open-source FPGA to embark on your secure computing project.
This makes for a fully open, vendor-agnostic compute machine, where all hardware is free from backdoor spying, and all dev tools and IP sources have nothing to hide.
Can it be more open and, by extension, more secure than this?! If you can think of a security gap, or an improvement, we are here to listen.
This project has more than one goal:
- Our first and primary goal is to write a solid suite of practical and appealing examples for the already-existing GateMate boards.
- Secondary goal is to design an open source ULX5M board with GateMate FPGA and CM4 compatibility. i.e. in the same form-factor as ULX4M.
- We also plan on testing Betrusted SoC waters with GateMate.
- The ultimate goal is to introduce CologneChip to the open community ecosystem and help GateMate take off from its launch ramp.
This project is currently in the execution phase — Follow us on:
https://github.com/chili-chips-ba/openCologne
With both ULX4M and BB3-CM4 already under NLnet umbrella, we are grateful to NLnet for having helped us transform this idea to reality.
