openENOC is an open hardware initiative aiming to deliver a modular, scalable, Ethernet-based Network-On-Chip (NOC) architecture tailored for FPGA SoCs. Unlike traditional NOC solutions that routinely use MxN mesh interconnects, custom or proprietary, openENOC would adopt Ethernet Layer 2 as its internal transport protocol. That enables straightforward integration with existing Ethernet infrastructure, and fosters a unified programming and communication model for both on-chip and off-chip systems with MAC address switching at its heart.
The idea came from the practical challenges observed during the development of the NLnet WireGuard FPGA project (grant agreement No101069594, https://github.com/chili-chips-ba/wireguard-fpga), where the need to scale cryptographic workloads (e.g., Curve25519, ChaCha20Poly1305) revealed limitations in conventional interconnect schemes.
openENOC intends to address these limitations by introducing an Ethernet-based interconnect that facilitates network-friendly scaling of cryptographic, edge computing and AI acceleration applications.
openENOC plans to deliver a full-stack, reusable hardware-software gateware developed in SystemVerilog and C/C++, and in alignment with open hardware and open-source software principles. Its ultimate goal is to open the floodgate for networked reconfigurable computing, in a way that’s accessible, reusable, portable and adaptable to a wide variety of workloads.
The modularity of the design will enable gradual adoption, customization and extension, making it suitable for educational, research, industrial, hobbyists and makers’ community at large.
This project is in the conceptual definition phase. Stay tuned for updates.
